1. Field of the Invention
The present invention relates to integrated circuit memory design, and more particularly to circuitry for providing on chip redundancy for high density memory arrays such as mask read only memory ROM.
2. Description of Related Art
In the manufacture of integrated circuit memory devices, it is common to provide a redundant segment of memory in addition to the main array, which can be used as a replacement for defective segments of the array. Thus, additional rows or columns of memory cells are provided on an integrated circuit memory device. After manufacturing of the device, it is tested to determine whether all segments of the main array are in good condition. If any segment of the array fails the testing, then it may be replaced by the redundant segment by storing an address on the chip characterizing the failed segment, and, using circuitry which is responsive to the stored address to access the additional segment in place of the defective one. This process significantly improves manufacturing yield for memory circuits.
Substantial prior art in this field is represented for instance by U.S. Pat. No. 3,753,244, U.S. Pat. No. 4,047,163, U.S. Pat. No. 4,250,570, and publications such as McKinney, "A 5V 64K EPROM Utilizing Redundant Circuitry", 1980 IEEE International Solid-State Circuits Conference, pages 146-147.
One field in which redundancy has not been widely applied is in the field of high density read-only memory ROM devices, such as mask ROM. Because the ROM cells in a mask ROM are programmed using a manufacturing step, it is impossible to use other mask ROM cells as an additional replacement segment. This is true because the additional segment of ROM cells can not be programmed after testing with the data from the failed segment. Thus, unlike programmable memory devices, in which the memory elements of the array are designed to be programmed after manufacturing, and in which redundant elements are easily utilized, read-only memory circuits do not readily allow the use of redundancy.
It has been proposed to use single polysilicon floating gate transistors as redundancy elements for mask ROM. See for example, co-pending U.S. Patent application entitled MEMORY REDUNDANCY CIRCUIT USING SINGLE POLYSILICON FLOATING GATE TRANSISTORS AS REDUNDANCY ELEMENTS, invented by Yiu, et al., filed Apr. 2, 1997, having application Ser. No. 08/825,873 (PCT application number PCT/US96/17300). One problem associated with the layout of floating gate transistors as redundancy elements for mask ROM is that the mask ROM is a very dense memory structure. Thus, in order to fit within the array structure of a mask ROM array, the floating gate redundancy elements must be laid out in a very compact fashion. This has prevented efficient implementations of mask ROM arrays with floating gate redundancy elements in the prior art. However, an EPROM like cell based on a single layer polysilicon floating gate transistor, that is programmed by hot electron injection is a good way to replace abnormal core cells in a mask ROM array.
As the density of memory arrays shrinks, and the need to improve yield is increased, applying redundant elements to read-only memory devices is desired. However, the redundant elements must be compact and compatible with the ROM manufacturing process, so that the cost of implementing the redundant elements does not outweigh any gains in manufacturing yield achieved by the redundancy.